Functional clock switching, such as during a mode change, can cause current jumps that exceed a power management system's reaction capability, resulting in a system reset or failure. In order to counteract this problem, a power management system is either overdesigned, or alternatively, a clock frequency during switching is stepped from a start frequency to a target frequency. The frequency step sizes can be controlled by either switching between multiple clock generators or by controlling frequency division stages in a Phase Locked Loop (PLL). These frequency step sizes are limited by an upper frequency of the PLL and a number of integer steps in the divider circuitry. Fractional division is an option, but an average clock period is generated using a combination of low and high period clocks. While the resulting average current jump is lower, peak current jumps remain unchanged. Thus, there is a need for generation of smaller current jumps with reasonable granularity.